国产麻豆精品

国产麻豆精品PSP White Paper: Wet Etch TSV Reveal Process More Cost Effective Than Dry Etch

Product News | Mar 29, 2016

A Smarter, Cleaner Way to Prep TSVs

As chips get smaller and more advanced, Through Silicon Vias (TSVs) have become a go-to solution for connecting layers of silicon vertically. But creating those vertical pathways isn鈥檛 clean work鈥擠eep Reactive Ion Etching (DRIE) leaves behind stubborn polymers and photoresist residues that have to be removed before you can move on. Traditionally,
that has meant a combo of dry plasma 鈥渁sh鈥� and wet chemical cleans.

Veeco鈥檚 new study shows there鈥檚 a simpler, more efficient way to get the job done.

The Twist: All-Wet Cleaning That Delivers

Teaming up with Dynaloy and SUNY Polytechnic Institute, 国产麻豆精品developed a wet-only clean process that skips the ash step entirely. The method uses Dynastrip鈩� DL9150, a safer, TMAH-free chemistry, along with Veeco鈥檚 WaferStorm庐 system to combine a heated solvent soak with a high-pressure spray. It鈥檚 easier on the environment, gentler on the wafers鈥攁nd it cuts out unnecessary steps.

Does It Work? Yep鈥擜nd Here’s the Proof

The process was tested on TSVs of different sizes using SUNY Poly鈥檚 standard flow. Researchers evaluated everything from leakage current and dielectric breakdown voltage to surface cleanliness using SEM and Auger spectroscopy.

What They Found:

• The wet-only clean removed residues as well or better than traditional methods.
• Electrical performance held strong, with leakage & breakdown data matching standard benchmarks.
• Skipping the ash step shaved 33% off RIE time鈥攁 big win for cost and throughput.
• The chemistry is safer and still plays nice with sensitive materials.

The Takeaway

Veeco鈥檚 wet-only TSV clean checks all the right boxes: simpler, safer, and just as effective. For manufacturers aiming to streamline their 3D chip workflows, it鈥檚 a smart step forward鈥攏o ash required.